1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that performs an alternative access to a redundant bit line instead of a defective bit line when a column address to be accessed indicates the defective bit line.
2. Description of Related Art
In a semiconductor memory device exemplified by DRAM (Dynamic Random Access Memory), a word line is selected based on a row address and a bit line is selected based on a column address, thereby accessing a memory cell arranged at an intersection of these lines. However, along with the recent increase in the memory capacity of semiconductor memory devices, some defective word lines and defective bit lines that do not operate properly are inevitably included in the semiconductor memory devices. Therefore, it is essential to incorporate a row relief circuit and a column relief circuit that relieve defects by replacing defective word lines or defective bit lines respectively by redundant word lines or redundant bit lines.
When a row address indicates a defective word line, a redundant word line is selected under control of the row relief circuit. Similarly, when a column address indicates a defective bit line, a redundant bit line is selected under control of the column relief circuit. Therefore, the row relief circuit starts an address comparing operation in response to the row address, and the column relief circuit starts an address comparing operation in response to the column address.
Because the number of memory cells connectable to one word line or one bit line is limited, a memory cell array is divided into a plurality of memory mats or memory blocks in semiconductor memory devices of recent years. A memory mat refers to a range extending one word line and one bit line. When the memory cell array is divided into a plurality of memory mats, a memory mat to be selected is determined by a row address, and therefore apart of an operation of the column relief circuit can be started at the time of supplying the row address (see Japanese Patent Application Laid-open No. H5-28794).
However, the supply of the row address is not necessarily accompanied by the supply of the column address. That is, in a normal access, a row address is supplied in response to an active command, and a column address is supplied next in response to a read command or a write command. In a refresh operation, only row addresses (refresh addresses) are supplied from a refresh counter without any subsequent supply of column addresses.
Therefore, in the refresh operation, it is not necessary for the column relief circuit to start an address comparing operation in response to the supply of row addresses. Such an operation rather causes unnecessary current consumption. This problem occurs not only to refresh operations but also to all operations commonly for which any column access is not necessary after a row access.